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Instruction completion: Reg[IR[20-16]] = ALUOut. 38. By the end of the second cycle the FSM will recognize the opcode. We add the Op='lui', a new transition condition from state 1 to a new state 10. In this state we perform the left shifting of the immediate field: ALUSrcA = x, ALUSrcB = 10, ALUOp = 11 (assume this means left shift of ALUSrcB). State 10 corresponds to cycle 3. Cycle 4 will be translated into a new state 11, in which RegDst = 0, RegWrite, MemtoReg = 0. State 11 will make the transition back to state 0 after completion.

It takes 100 ps * 106 instructions - 100 microseconds to execute on a nonpipelined processor (ignoring start and end transients in the pipeline). b. A perfect 20-stage pipeline would speed up the execution by 20 times. c. Pipeline overhead impacts both latency and throughput. 4 There is a data dependency through $ 3 between the first instruction and each subsequent instruction. There is a data dependency through $ 6 between the 1 w instruction and the last instruction. 7, the data dependencies between the first instruction and each subsequent instruction can be resolved by using forwarding.

In that time Ml can run (400 seconds/{5 seconds/iteration)) = 80 iterations of P2. M2 can run (1200 seconds/(10 seconds/iteration)) = 120 iterations. Thus M2 performs better on this workload. 67 per (iteration/hour) for M2. Thus Ml is most cost-effective. 7 a. 2 seconds b. 2 seconds/3 seconds or 40% of the total CPU time. 8 The ideal instruction sequence for PI is one composed entirely of instructions from class A (which have CPI of 1). So Mi's peak performance is (4 x 109 cydes/second)/( 1 cycle/instruction) = 4000 MIPS.

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Computer Organization And Design - The Hardware Software Interface. Solutions by Hennessy, Patterson


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