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By Paul R. Gray
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Positive voltage VDs causes the reverse bias from the drain to the substrate to be larger than from the source to substrate, and thus the widest depletion region exists at the drain. For simplicity, however, we assume that the voltage drop along the channel itself is small so that the depletion-layer width is constant along the channel. The drain current ID is where d Q is the incremental channel charge at a distance y from the source in an incremental length d y of the channel, and d t is the time required for this charge to cross length dy.
27. The gate and substrate then form the plates of a capacitor with the SiOz as a dielectric. Positive charge accumulates on the gate and negative charge in the substrate. 2 for a pn-junction. The depletion region is shown in Fig. 27. 2 can now be applied. 10), the depletion-layer width X under the oxide is a) where 4 is the potential in the depletion layer at the oxide-silicon interface, NA is the doping density (assumed constant) of the p-type substrate in atoms/cm3, and E is the permittivity of the silicon.
10), the depletion-layer width X under the oxide is a) where 4 is the potential in the depletion layer at the oxide-silicon interface, NA is the doping density (assumed constant) of the p-type substrate in atoms/cm3, and E is the permittivity of the silicon. 27 Idealized NMOS device cross section with positive Vc5 applied, showing depletion regions and the induced channel. '^ The Fermi level 4f is defined as where k is Boltzmann's constant. Also, ni is the intrinsic carrier concentration, which is where E, is the band gap of silicon at T = O•‹K, Nc is the density of allowed states near the edge of the conduction band, and Nv is the density of allowed states near the edge of the valence band, respectively.
Analysis and Design of Analog Integrated Circuits by Paul R. Gray