Richard L. Sites, Richard T. Witek's Alpha AXP Architecture Reference Manual PDF
By Richard L. Sites, Richard T. Witek
Alpha AXP structure Reference guide
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The PC is an implied operand on conditional branch and subroutine jump instructions. The PC is not accessible as an integer register. 2 Integer Registers There are 32 integer registers (RO through R31), each 64 bits wide. Register R31 is assigned special meaning by the Alpha AXP architecture. When R31 is specified as a register source operand, a zero-valued operand is supplied. For all cases except the Unconditional Branch and Jump instructions, results of an instruction that specifies R31 as a destination operand are discarded.
The usage of those fields depends on the instruction. 11. 3. 2 Branch Instruction Format The Branch format is used for conditional branch instructions and for PC-relative subroutine jumps. It has the format shown in Figure 3-3. Figure 3-3: Branch Instruction Format 31 2120 26 25 Opcode Ra 0 Branch_disp A Branch format instruction contains a 6-bit opcode field, one 5-bit register address field (Ra), and a 21-bit signed displacement field. 3-10 Common Architecture (I) The displacement is treated as a longword offset.
1 Subsetting Rules An instruction that is omitted in a subset implementation of the Alpha AXP architecture is not performed in either hardware or PALcode. System software may provide emulation routines for subsetted instructions. 1 Floating-Point Subsets Floating-point support is optional on an Alpha AXP processor. An implementation that supports floating-point must implement the 32 floating-point registers, the Floating-point Control Register (FPCR) and the instructions to access it, floatingpoint branch instructions, floating-point copy sign (CPYSx) instructions, floatingpoint convert instructions, floating-point conditional move instruction (FCMOV), and the S_floating and T_floating memory operations.
Alpha AXP Architecture Reference Manual by Richard L. Sites, Richard T. Witek